| 摘要 |
An N-bit (e.g. N = 4) memory 100 is coupled to a first bus 600. A second memory 200 is coupled by a coupling circuit 300, e.g. a multiplexer, to the first bus 600 and a second bus 700. In a first mode, the second memory 200 is coupled to the first bus 600 and an accessing circuit 400 provides control signals 410, 420 selectively to the first and second memories so that, whichever memory is accessed, reads out data on to the first bus 600. In a second mode, the control circuit 500 causes the coupling circuit to couple the second memory 200 to the second bus 700. The accessing circuit 400 applies control signals 410, 420, simultaneously to the two memories so that each access causes data to be read out from the first and second memories simultaneously on to the first and second buses respectively. |
