| 摘要 |
<p>Cache devices are provided for respective processors, interconnected through a common connection network, and connected to a main memory. Each cache memory stores part of the data in the main memory in units of one cache line and sets the state tag of, for example, an MESI protocol, used for data consistency control, for every cache line. If a prefetch request occurs accompanying a read request made by a processor, a cache controller executes a weak read operation for causing the prefetch request to fail as a prefetch protocol when the data stored in other cache devices cannot be read unless the state tag is changed. Moreover, the cache controller reads prefetch data without changing the state tag of the other cache devices and stores the data in a weak read state W. The data in a weak read state is made ineffective through a memory-consistency sync operation by a software. Moreover, the cache controller stores the prefetch data in a cache in a passive storage mode, and it does not report the storage of the prefetch data even if the prefetch data is required to be read by another cache unit.</p> |
