| 摘要 |
The present invention provides a method for fabricating a semiconductor device capable of securing a bottom contact area of a storage node contact as well as of preventing losses of a bit line hard mask insulation layer. These effects are achieved by planarizing an inter-layer insulation layer, which is filled into etched portions formed between conductive patterns, with the bit line hard mask insulation layer through a CMP process. This planarization process decreases a thickness of an etch target to thereby provide more vertical etch profile compared to a typical etch profile that is tapered or inclined at a bottom contact area. As a result of the decreased thickness of the etch target and the more vertical etch profile, it is possible to obtain the wider bottom contact area and prevent losses of the bit line hard mask insulation layer. |
