发明名称 |
Method for manufacturing semiconductor devices |
摘要 |
A method for manufacturing semiconductor devices includes a step of etching a sample including an interlayer insulating layer containing Al<SUB>2</SUB>O<SUB>3 </SUB>and a polysilicon or SiO<SUB>2 </SUB>layer in contact with the interlayer insulating layer using a plasma etching system. The interlayer insulating layer is etched with a gas mixture containing BCl<SUB>3</SUB>, Ar, and CH<SUB>4 </SUB>or He. The gas mixture further contains Cl<SUB>2</SUB>. The interlayer insulating layer is etched in such a manner that a time-modulated high-frequency bias voltage is applied to the sample. The interlayer insulating layer is etched in such a manner that the sample is maintained at a temperature of 100° C. to 200° C. The interlayer insulating layer and the polysilicon or SiO<SUB>2 </SUB>layer are separately etched in different chambers.
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申请公布号 |
US7364956(B2) |
申请公布日期 |
2008.04.29 |
申请号 |
US20050209653 |
申请日期 |
2005.08.24 |
申请人 |
HITACHI HIGH-TECHNOLOGIES CORPORATION |
发明人 |
SAITO GO;NISHIDA TOSHIAKI;SHIMOMURA TAKAHIRO;ARASE TAKAO |
分类号 |
H01L21/336 |
主分类号 |
H01L21/336 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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