发明名称 Buffer insertion to reduce wirelength in VLSI circuits
摘要 Wirelength in a net of an integrated circuit design is reduced by forming clusters of sinks to be interconnected, inserting a buffer at each cluster, and providing branch connections between clusters by connecting a sink of one cluster to a buffer of another cluster, to create a buffer tree spanning all sinks. The buffers are inserted at a point on a respective bounding box of a cluster that is closest to a source for the net. A sink that provides a branch connection to the buffer of another cluster is the closest sink to that buffer (except for those sinks in the cluster). Clusters may be formed by examining different pairs of the sinks with different bounding boxes, and identifying one of the pairs whose bounding box has a lowest half-perimeter as the best pair for clustering.
申请公布号 US7484199(B2) 申请公布日期 2009.01.27
申请号 US20060383544 申请日期 2006.05.16
申请人 INTERNATIONAL BUSINESS MACHINES CORPORATION 发明人 ALPERT CHARLES J.;MAHMUD TUHIN;QUAY STEPHEN T.
分类号 G06F17/50 主分类号 G06F17/50
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