| 摘要 |
PURPOSE:To obtain a phase locked loop circuit in which a time required for synchronization is short and jitter in an output clock is reduced. CONSTITUTION:The circuit is provided with a switch 7 selecting a clock CKO and a frequency division signal SD respectively as signal CA in response to each of non-supplied/supplied lock detection signal L and a switch 8 selecting a clock CKR and the CKO as signal I respectively. A VCO 4A is provided with variable delay circuits 41 to 44 whose delay time changes with a control signal CC and a switch 45 switching signals O1, O2 and O4 depending on the supply of the lock detection signal L. Then the VCO 4A acts as a delay circuit delaying variably the signal I when the lock detection signal L is not received in response to the control signal CC and acts as a VCO controlling the frequency of the clock CKO in response to the signal CC when the lock detection signal L is received.
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