Methods and apparatus for performing fast multiplication operations in bit-serial processors

摘要

Bit-serial processors quickly multiply multiple-bit operands using significantly fewer clock cycles as compared to conventional bit-serial implementations. Exemplary embodiments process groups of operand bits simultaneously to provide the significant speed increases. Advantageously, however, the exemplary embodiments utilize logic and memory architectures which are fully compatible with, and fully useful for, conventional bit-serial applications, and the embodiments thus provide fast multiple-bit multiplications while at the same time providing all of the advantages typically associated with conventional bit-serial processors.