Router and switch architecture

摘要

A packet switching system for a packet transfer network, the system having an architecture including a plurality of line cards, each including an ingress path pipeline, with processing elements, and an egress buffer, and an electro-optical In/Out (IO) interconnect coupling the line cards to one another in a full mesh connectivity, in the absence of a switch fabric, wherein the ingress path pipeline of each line card is coupled by means of the electro-optical IO interconnect to the egress buffer of each of the plurality of line cards.

主权项

1. A packet switching system for a packet transfer network comprising:
a plurality of line cards, each line card comprising an ingress path pipeline and an egress buffer; and an electro-optical In/Out (IO) interconnect coupling the ingress path pipeline of each line card to the egress buffer of the other line cards, wherein said electro-optical IO interconnect includes:
a CMOS chip with logic circuitry coupled to a matrix of vertical-cavity surface-emitting lasers (VCSELs) and to a matrix of Photo Detectors (PDs), andinterface circuitry between the logic circuitry on said CMOS chip and said matrix of VCSELs, and between the logic circuitry on said CMOS chip and said PDs; wherein the ingress path pipeline of each line card is configured to:
i) receive a packet from the packet transfer network,ii) perform ingress processing on the received packet,iii) perform partial egress processing on the received packet, including classifying and identifying the egress destination address,iv) attach data to the received packet identifying any additional egress processing still required for the packet, andv) send the processed packet to the egress buffer of another line card using the electro-optical IO interconnect.