| 摘要 |
An extensible and configurable FPGA storage structure and an FPGA device. The FPGA storage structure comprises: multiple local storage units, a controller and two clock buffers. The two clock buffers are respectively used for providing different clock signals to two clock input ports of the controller. The controller is used for receiving an externally input write address signal and generating, under the drive of the clock signals, multiple enabling signals and a write address decoding signal output to the multiple local storage units. The local storage units comprise a local memory and a gate for providing input data to the local memory. Based on a configuration mode of each of the local storage units, according to the enabling signals, the input write address decoding signal or a read address signal and the input data, and output data under a corresponding configuration mode is generated. By using the storage structure to implement the design of a memory with a medium capacity, not only can additional logical resource consumption be avoided, but also storage resource waste caused by the use of a block memory is avoided. |
