| 发明名称 |
Packaging for eight-socket one-hop SMP topology |
| 摘要 |
A mechanism is provided for packaging a multiple socket, one-hop symmetric multiprocessor topology. The mechanism connects each of a first plurality of processor modules to a first multiple-socket planar via a respective one of a first plurality of land grid array (LGA) connectors. The mechanism connects the first multiple-socket planar to a first side of a redistribution card via a second plurality of LGA connectors. The mechanism connects each of a second plurality of processor modules to a second multiple-socket planar via a respective one of a third plurality of LGA connectors. The mechanism connects the second multiple-socket planar to a second side of the redistribution card via a fourth plurality of LGA connectors. |
| 申请公布号 |
US9456506(B2) |
申请公布日期 |
2016.09.27 |
| 申请号 |
US201314136135 |
申请日期 |
2013.12.20 |
| 申请人 |
International Business Machines Corporation |
发明人 |
Colbert John L.;Dreps Daniel M.;Harvey Paul M.;Mandrekar Rohan U. |
| 分类号 |
H05K3/32;G06F1/18;H05K7/10;G06F1/20;H01L25/10;H01L23/36;H01L23/498 |
主分类号 |
H05K3/32 |
| 代理机构 |
|
代理人 |
Tkacs Stephen R.;Walder, Jr. Stephen J.;Petrokaitis Joseph |
| 主权项 |
1. A multiple socket, one-hop symmetric multiprocessor package, comprising:
a first multiple-socket planar; a second multiple-socket planar; a redistribution card; a first plurality of processor modules connected to the first multiple-socket planar via a respective one of a first plurality of land grid array (LGA) connectors, wherein the first multiple-socket planar is connected to a first side of the redistribution card via a second plurality of LGA connectors; and a second plurality of processor modules connected to the second multiple-socket planar via a respective one of a third plurality of LGA connectors, wherein the second multiple-socket planar is connected to a second side of the redistribution card via a fourth plurality of LGA connectors. |
| 地址 |
Armonk NY US |
