发明名称 SEMICONDUCTOR DEVICE AND TEST METHOD FOR SEMICONDUCTOR DEVICE
摘要 PROBLEM TO BE SOLVED: To provide a semiconductor device which can shorten a test time for plural memory circuits in which capacity is different. SOLUTION: Plural memory circuits 2, 3 and an address discriminating circuit 4 are formed on a substrate 1 of a semiconductor device. Plural memory circuits 2, 3 are set to different capacity, a test address signal TADR is inputted simultaneously at the time of a test, and tests are performed simultaneously by a test address signal TADR. An address discriminating circuit 4 is provided corresponding to the memory circuit 3, and the test address signal TADR is inputted to it. The address discriminating circuit 4 judges whether the test address signal TADR is valid for the memory circuit 3 or not. And the address discriminating circuit 4 outputs a discrimination signal based on a discriminated result, when the test address signal TADR does not coincide with an address signal required for the memory circuit 3, memory operation based on the test address signal is prohibited.
申请公布号 JPH11203893(A) 申请公布日期 1999.07.30
申请号 JP19980000176 申请日期 1998.01.05
申请人 FUJITSU LTD;FUJITSU VLSI LTD 发明人 ITO EISAKU;ITAKURA KATSUHIKO;YANAGIDA HIROYOSHI
分类号 G01R31/28;G11C29/00;G11C29/02;G11C29/56 主分类号 G01R31/28
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