发明名称 PERIPHERAL CONTROL PROCESSOR
摘要 PROBLEM TO BE SOLVED: To provide a peripheral control processor capable of eliminating necessity for normally re-transferring whole data in the case of software retrial and or shortening a processing time as compared with that in a conventional manner. SOLUTION: The peripheral control processor 8 is provided with a low-order interface control part 6 controlling an interface with a peripheral device 7 which is controlled by a peripheral control processor 8, a track buffer 4 for temporarily storing input/output data with respect to the peripheral device 7, a fault information control part 5 for analyzing fault information which is announced from the peripheral device 7, a data transfer control part 3 for controlling input/output data transfer and a high-order interface control part 1 for controlling the interface with respect to a host device 1. Transfer is started by using data of the track buffer 4 in the case of a software retrying operation, fault information is analyzed and the retrying operation from a fault occurrence logical block address to the peripheral device 7 is executed.
申请公布号 JP2000181810(A) 申请公布日期 2000.06.30
申请号 JP19980356660 申请日期 1998.12.15
申请人 NEC IBARAKI LTD 发明人 TANAKA YASUSHI
分类号 G06F13/00;(IPC1-7):G06F13/00 主分类号 G06F13/00
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