发明名称 DUPLEX SYSTEM AND MEMORY CONTROL METHOD
摘要 PROBLEM TO BE SOLVED: To match the content of the cache memory of an act system with the contents of main memories in two systems and to easily switch systems in the duplex system of a zero system and a one system, containing processors having the cache memories and in a memory control method. SOLUTION: In the duplex system of a zero system and a one system containing processors 1 and 11 having cache memories 2 and 12, cache memory control circuits 9 and 19 reading the contents of cache memories 2 and 12 issuing coherent read cycles for reading the contents of he cache memories 2 and 12 and reading them in main memories 4 and 14 with periodical starting or starting by an urgent control signal by a power cut and the detection of processor runaway are connected to local buses 7 and 17. Bus control circuits 5 and 15 preferentially give the use permission of local buses 7 and 17 with the urgent control signals, the contents of the cache memories are written into the main memories, and they are written into the main memories of a mate system through a cross bus 10. Then, the contents of the main memories 4 and 14 of the two systems are matched.
申请公布号 JP2000181738(A) 申请公布日期 2000.06.30
申请号 JP19980361588 申请日期 1998.12.18
申请人 FUJITSU LTD 发明人 TAHIRA FUMIAKI
分类号 G06F12/08;G06F11/20;(IPC1-7):G06F11/20 主分类号 G06F12/08
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