发明名称
摘要 <p>PROBLEM TO BE SOLVED: To increase operation speed by making a cycle time TCY shorter than an address access time TAC in a semiconductor memory like a mask ROM. SOLUTION: Address signals A1-A19 outputted in order an address buffer 241 to which externally supplied address signals A1-A19 are inputted are stored in order in two address storage circuits 242 and 243. Address signals A1-A19 outputted from these two address storage circuits 242 and 243 are decoded, data is read out from two memory regions (one memory region in memory cell arrays 246 and 247, another memory region in memory cell arrays 248 and 249), and data read out from these two memory regions are switched in order by an output switching circuit 254 and outputted.</p>
申请公布号 JP3580266(B2) 申请公布日期 2004.10.20
申请号 JP20010133835 申请日期 2001.05.01
申请人 发明人
分类号 G11C17/00;G11C17/18;(IPC1-7):G11C17/00 主分类号 G11C17/00
代理机构 代理人
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