| 摘要 |
<p><P>PROBLEM TO BE SOLVED: To reduce manufacturing costs per unit megabyte in a memory to less than half and more than one tenth the manufacturing costs of a circuit commonly manufactured by a monolithic circuit integration method simply. <P>SOLUTION: In a three-dimensional (3DS) memory 100, a memory circuit 103 and a control logic circuit 101 can be physically separated onto each layer 103 to optimize each layer separately. For several memory circuits 103, one control logic circuit 101 is sufficient, thus reducing the costs. The manufacture of the 3DS memory 100 has a step of thinning the thickness of the memory circuit 103 to not more than 50μm, and a step of joining the memory circuit to a circuit laminate in a wafer substrate form. A high-density interlayer vertical bus interconnection section 105 of particulates is used. A method of manufacturing the 3DS memory 100 enables some performance and physical size efficiency and is executed by an established semiconductor machining technique. <P>COPYRIGHT: (C)2008,JPO&INPIT</p> |
