SEMICONDUCTOR DEVICE

摘要

A semiconductor device may include a mat array, and a plurality of memory cell mats each including bit lines. The memory cell mats may be included in the mat array. The semiconductor device may include edge sense amplifier blocks comprising edge sense amplifiers coupled to half of the bit lines of the outermost memory cell mats among the memory cell mats. The half of the bit lines of the outermost memory cell mats may be coupled to the edge sense amplifiers, respectively, and may be configured for a first input. The semiconductor device may include half dummy mats each having an area corresponding to half of the area of a memory cell mat of the plurality of memory cell mats and configured to provide reference bit lines for a second input to the edge sense amplifiers, respectively.

主权项

1. A semiconductor device comprising:
a mat array; a plurality of memory cell mats each including bit lines, the memory cell mats included in the mat array; edge sense amplifier blocks comprising edge sense amplifiers coupled to half of the bit lines of the outermost memory cell mats among the memory cell mats, wherein the half of the bit lines of the outermost memory cell mats are coupled to the edge sense amplifiers, respectively, and are configured for a first input; and half dummy mats each having an area corresponding to half of the area of a memory cell mat of the plurality of memory cell mats and configured to provide reference bit lines for a second input to the edge sense amplifiers, respectively, wherein each of the reference bit lines is configured by coupling bit lines within the half dummy mat by two.