MULTI-BIT FULL ADDER BASED ON RESISTIVE-SWITCHING DEVICES AND OPERATION METHODS THEREOF

摘要

The present disclosure discloses a full adder based on resistive-switching devices and an operation method thereof. A multi-bit full adder circuit is constituted by using a cross-bar array of resistive-switching devices, wherein data of standard sums is stored on the principle diagonal of the cross-bar array in a nonvolatile manner, and carry data is stored in adjacent units on both sides of the principle diagonal. The carry data is stored according to whether the storage loop (crosstalk loop) is turned on. With the present disclosure, the multi-bit full adder circuit is significantly simplified. Thereby, additional circuits for generating a carry signal are reduced, the circuit delay and chip area are decreased, and the adder has an ability of nonvolatile storage.

主权项

1. A multi-bit full adder based on resistive-switching devices, comprising:
N word lines arranged in parallel, wherein N is larger than or equal to 3 and 1st to N−1th word lines of the N word lines respectively correspond to one of an N−1-bit addend and an N−1-bit augend; N word line gating devices respectively connected to corresponding word lines; N bit lines arranged in parallel and placed across the word lines arranged in parallel, wherein 1st to N−1th bit lines of the N bit lines respectively correspond to the other of the N−1-bit addend and the N−1-bit augend; N bit line gating devices respectively connected to corresponding line lines; N*N resistive-switching units each being located in a crossing point of a corresponding word line and a corresponding bit line and being connected to the corresponding word line and the corresponding bit line, wherein each resistive-switching unit has a first resistance state, a second resistance state, a third resistance state, and a fourth resistance state, and a resistance value in the first resistance state is less than a resistance value in the second resistance state, the resistance value in the second resistance state is less than a resistance value in the third resistance state, and the resistance value in the third resistance state is less than a resistance value in the fourth resistance state, where the first resistance state and the third resistance state represent “0” and the second resistance state and the fourth resistance state represent “1”; wherein, in data input through the word lines, input “1” represents a positive level pulse, and input “0” represents a zero level pulse, in data input through the bit lines, input “1” represents a negative level pulse, and input “0” represents a zero level pulse, a standard sum of an ith bit of the addend and an ith bit of the augend is stored in a resistive-switching unit in an ith row and an ith column of the array of resistive-switching units in a nonvolatile manner, and a carry value is determined according to resistance states of the resistive-switching unit in the ith row and the ith column, a resistive-switching unit in the ith row and an i+1th column, and a resistive-switching unit in an i+1th row and the ith column in the array of resistance-switching units.