| 摘要 |
A method, apparatus, and computer program product for performing verification on an integrated circuit design having state variables. Random vectors are generated, used to simulate the design, and generate a set of values for the state variables. The generated values are compared to groups having stored values from previous stimulations and either a new group is crated for the generated set of values or the existing groups accurately represent the generated set of values and they are stored in one of the existing groups.
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