| 发明名称 | Semiconductor device for parallel bit test and test method thereof | ||
| 摘要 | A semiconductor device includes a plurality of memory chips and a plurality of signal selection units respectively corresponding to the plurality of memory chips, and suitable for commonly transferring test data signals from an external to a corresponding one of the plurality of memory chips during a common test mode, wherein one or more of the plurality of signal selection units may transfer the test data signals from the external to corresponding ones of the plurality of memory chips during an individual test mode, and wherein the semiconductor device may be set to the common test mode when a common test signal is enabled, and set to the individual test mode when both the common test signal and a test control signal are enabled. | ||
| 申请公布号 | US9362005(B2) | 申请公布日期 | 2016.06.07 |
| 申请号 | US201414477618 | 申请日期 | 2014.09.04 |
| 申请人 | SK Hynix Inc. | 发明人 | Ko Jae-Bum;Byeon Sang-Jin |
| 分类号 | G01R31/02;G11C29/26;G11C8/12;G11C29/56 | 主分类号 | G01R31/02 |
| 代理机构 | IP & T Group LLP | 代理人 | IP & T Group LLP |
| 主权项 | 1. A semiconductor device, comprising: a plurality of memory chips; and a plurality of signal selection units respectively corresponding to the plurality of memory chips, and suitable for commonly transferring test data signals from an external to a corresponding one of the plurality of memory chips during a common test mode, wherein one or more of the plurality of signal selection units transfer the test data signals from the external to corresponding ones of the plurality of memory chips during an individual test mode, and wherein the semiconductor device is set to the common test mode when a common test signal is enabled, and set to the individual test mode when both the common test signal and a test control signal are enabled. | ||
| 地址 | Gyeonggi-do KR | ||