发明名称 Methods and apparatus for designing and constructing dual write memory circuits with voltage assist
摘要 Static random access memory (SRAM) circuits are used in most digital integrated circuits to store representations of data bits. To handle multiple concurrent memory requests, an efficient dual-port six transistor (6T) SRAM bit cell is proposed. The dual-port 6T SRAM cell uses independent word lines and bit lines such that the true/data side and the false/data-complement side of the SRAM bit cell may be accessed independently. Single-ended reads allow the two independent word lines and bit lines to handle two independent read operations in a single cycle using spatial domain multiplexing. Single-ended writes are enabled by adjusting the VDD power voltage supplied to a memory cell when writes are performed such that a single word line and bit line pair can be used write either a logical “0” or logical “1” into either side of the SRAM bit cell.
申请公布号 US9520178(B2) 申请公布日期 2016.12.13
申请号 US201514831008 申请日期 2015.08.20
申请人 Cisco Technology, Inc. 发明人 Iyer Sundar;Chuang Shang-Tse;Nguyen Thu
分类号 G11C7/22;G11C11/419;G11C11/412;G11C11/413;G11C8/16 主分类号 G11C7/22
代理机构 Edell, Shapiro & Finnan, LLC 代理人 Edell, Shapiro & Finnan, LLC
主权项 1. A dual-port random access memory system, comprising: a memory array comprising a plurality of memory cells, each of the plurality of memory cells comprising a memory element coupled to a power line that provides an operation voltage to the memory element, each memory cell comprising: a first bidirectional memory port coupled to a data side of the memory element, the first bidirectional memory port controlled by a first word line for performing a first single-ended read or write operation, anda second bidirectional memory port coupled to a data-complement side of the memory element, the second bidirectional memory port controlled by a second word line for performing a second single-ended read or write operation; and a memory controller configured to control the operation voltage provided by the power line, wherein the memory controller is configured to increase the operation voltage to a normal power supply voltage when performing a read operation on the memory element and decrease the operation voltage to a reduced voltage level that is lower than the normal power supply voltage at other times.
地址 San Jose CA US