| 摘要 |
PROBLEM TO BE SOLVED: To provide a memory synchronization system negating the need of intricate scheduling among a plurality of control boards and being capable of appropriately performing load distribution.SOLUTION: A memory synchronization system 10 includes: a plurality of control boards 11; a relay substrate 12; multiport memories (DPRAM) 22; and a relay CPU 31. The multiport memories are provided to the plurality of control boards. The multiport memories are provided with memory spaces 23 being of a number of the plurality of control boards or more. The multiport memories can be accessed from both of the plurality of control boards and the relay substrate. The relay CPU sequentially accesses the memory spaces where each control board in the multiport memories of the plurality of control boards can perform writing. The relay CPU determines data variations of the memory spaces. The relay CPU writes varied data in the memory space in the multiport memory of another control board when data of divided memory spaces are varied.SELECTED DRAWING: Figure 1 |
