发明名称 |
Memory subsystem for bitmap printer data controller |
摘要 |
A DRAM memory controller for a printer having a single host CPU and a bitmap memory. The CPU initiates data transfers synchronously to a system clock for filling the bitmap memory, and a DMA controller initiates data transfers asynchronously to the system clock for transferring data from the bitmap memory to a print engine. The controller includes a first sequencer for controlling synchronous data transfers initiated by the host CPU, a second sequencer for controlling asynchronous data transfers initiated by the DMA controller, a refresh request generator for generating a refresh request signal which is asynchronous to the system clock, and a third sequencer for controlling memory refresh and for controlling arbtitration betwween the first, second, and third sequencers. Also provided is a method of transferring data between a bitmap memory and a print fifo in a printer. The method includes the steps of initiating a single data write transfer to a location in a dynamic RAM; reading a word of data from the location in the dynamic RAM to a first buffer using a first page-mode DRAM access; and writing data from a second buffer to the same location in the dynamic RAM using a second page-mode DRAM access.
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申请公布号 |
US5511152(A) |
申请公布日期 |
1996.04.23 |
申请号 |
US19930124177 |
申请日期 |
1993.09.20 |
申请人 |
DIGITAL EQUIPMENT CORPORATION |
发明人 |
LAI, CHARLES C.;BORTMAN, WAYNE R. |
分类号 |
G06F13/16;G06K15/00;(IPC1-7):G06K15/00 |
主分类号 |
G06F13/16 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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