发明名称 PLL CIRCUIT
摘要 PROBLEM TO BE SOLVED: To provide a PLL circuit having a loop filter having the same lockup time in bidirectional channel switching and capable of preventing the reduction of a CN ratio. SOLUTION: The PLL circuit is provided with a reference oscillation circuit 2, a fixed frequency divider 3, a voltage controlled oscillator 7, a variable frequency divider 9, a phase comparator 4 and a charge pump circuit 5 for outputting a phase difference signal between an output signal from the divider 3 and an output signal from the divider 9 and a lock detection signal, a loop filter 6, and a lock detection circuit 10 for outputting a lock detection signal detecting signal. A switch circuit having plural capacitors and capable of switching a time constant by switching the connection state of these capacitors in accordance with a detection signal is connected to the loop filter 6. Thus lockup time can be set up to the same value independently of a channel switching direction without reducing a CN ratio.
申请公布号 JPH11103250(A) 申请公布日期 1999.04.13
申请号 JP19970262403 申请日期 1997.09.26
申请人 KYOCERA CORP 发明人 SAKAMOTO MASARU
分类号 H03L7/093 主分类号 H03L7/093
代理机构 代理人
主权项
地址