发明名称 ADDRESS GENERATOR AND MEMORY CONTROLLER
摘要 PROBLEM TO BE SOLVED: To record the collected data at a fixed interval for a period longer than the period that is scheduled at first by carrying up or down an address with the addition/subtraction operations of a prescribed system when the address has no overflow and has the overflow respectively. SOLUTION: When the address spaces 00h-FFh of 8 bits, for example, are supposed, an address generator of a write address generation means 101 generates the addresses by carrying them up by 00h and 01h respectively. A memory controller records successively the data D01 which are collected for the time 1 and at a time interval that is set at first on the addresses which are carried up one by one like the address 01h. When a writing operation reaches the address FFh, the address has the overflow and thereby the addresses are generated by carrying up every two addresses after starting at the addresses 01h and 03h and the addresses at and after the address 01h which is obtained by adding 1 to the head address 00h. Thus, the data collected successively at a double time interval are recorded on the addresses which are carried up every two addresses like a case where the data D102 collected at the time 102h are recorded on the address 03h.
申请公布号 JP2000285012(A) 申请公布日期 2000.10.13
申请号 JP19990089989 申请日期 1999.03.30
申请人 SEIKO EPSON CORP 发明人 ISHIDA TAKUYA
分类号 G06F12/02;(IPC1-7):G06F12/02 主分类号 G06F12/02
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