发明名称 Transistor array structure
摘要 A semiconductor circuit can include a plurality of arrays of transistors having differing characteristics and operating at low voltages and currents. A drain line drive signal may provide a potential to a drain line to which a selected transistor is connected. A row of drain mux circuits can provide reduced leakage current on the drain line drive signal so that more accurate current measurements may be made. A gate line drive signal may provide a potential to a gate line to which the selected transistor is connected. A column of gate line mux circuits can provide a gate line low drive signal to unselected transistors to reduce leakage current in unselected transistors so that more accurate drain current measurements may be made to the selected transistor.
申请公布号 US9449967(B1) 申请公布日期 2016.09.20
申请号 US201313835327 申请日期 2013.03.15
申请人 Fujitsu Semiconductor Limited 发明人 Roy Richard S.;Leshner Samuel
分类号 G01R31/00;G01R31/26;G11C7/00;H01L27/088 主分类号 G01R31/00
代理机构 Baker Botts L.L.P. 代理人 Baker Botts L.L.P.
主权项 1. A circuit, comprising: an array of transistors; a plurality of drain lines, each drain line coupled to a plurality of the array of transistors in a drain line direction; and a plurality of drain line multiplexers, each drain line multiplexer having a first drain multiplexer terminal coupled to a drain line drive signal, a second drain multiplexer terminal coupled to a leakage current reduction signal, and a third drain multiplexer terminal coupled to a corresponding one of the plurality of drain lines wherein each one of the plurality of drain line multiplexers includes a first pass gate having a first pass gate controllable impedance path coupled between the first drain multiplexer terminal and the third drain multiplexer terminal and a second pass gate having a second pass gate controllable impedance path coupled between the second drain multiplexer terminal and the third drain multiplexer terminal, and wherein when one of the plurality of drain line multiplexers provides a low impedance path between the first drain multiplexer terminal and the third drain multiplexer terminal, the other of the plurality of drain line multiplexers provides a low impedance path between the second drain multiplexer terminal and the third drain multiplexer terminal.
地址 Yokohama JP