MEMORY BIT CELL FOR REDUCED LAYOUT AREA

摘要

An approach for providing SRAM bit cells with miniaturized bit cells, without local interconnection layers, with improved lithographic printability, and enabling methodology are disclosed. Embodiments include providing first color structures, in a M1 layer, including a first word line, a first bit line, a second bit line, a first ground line, a second ground line, a second latch line or a combination thereof, wherein the first color structures include side edges longer than tip edges; providing second color structures, in the M1 layer, including a second word line, a first power line, a second power line, a first latch line or a combination thereof, wherein the second color structures include side edges longer than tip edges; and forming a bit cell including the first color structures and the second color structures, wherein adjacent tip edges include a first color structure tip edge and a second color structure tip edge.

主权项

1. A memory device comprising:
first color structures, in a metal1 (M1) layer, including a first word line, a first bit line, a second bit line, a first ground line, a second ground line, a second latch line or a combination thereof, wherein the first color structures include side edges longer than tip edges; second color structures, in the M1 layer, including a second word line, a first power line, a second power line, a first latch line or a combination thereof, wherein the second structures include side edges longer than tip edges; a bit cell including the first color structures and the second color structures, wherein adjacent tip edges include a first color structure tip edge and a second color structure tip edge; and an array of four bit cells including a first bit cell at a lower left position, a second bit cell at a lower right position, a third bit cell at an upper left position, and a fourth bit cell at an upper right position, wherein a layout of the second bit cell is a mirror image of a layout of the first bit cell, a layout of the third bit cell is same as the layout of the second bit cell, and a layout of the fourth bit cell is same as the layout of the first bit cell.