| 摘要 |
PROBLEM TO BE SOLVED: To provide a flip-flop circuit and a semiconductor integrated circuit device, capable of setting a hold margin of a scan chain circuit during a scan test while avoiding the sacrifice of performance during normal operation.SOLUTION: A flip-flop circuit comprises: a first gate PG1 operating on the basis of first edges of clocks CLK and CLKB; a first latch LAT1 holding an output of the first gate; a second gate PG2 operating on the basis of second edges of the clocks; a second latch LAT2 holding an output via the second gate; and a third gate PG3 provided in series to the second gate between the first latch and the second latch and controlled by a control signal which delayed the clocks.SELECTED DRAWING: Figure 5 |
