CLOCK DISTRIBUTION SCHEMES WITH WIDE OPERATING VOLTAGE RANGES

摘要

Clock distribution schemes with wide operating voltage ranges are disclosed. In one aspect, an operating voltage level or condition within a computing device is sensed. In a first voltage condition, delay elements are used within a clock tree to minimize clock skew. In a second voltage condition, one or more delay and/or clocked elements are bypassed to minimize clock skew at the second voltage condition. In addition to controlling clock skew, power may be conserved by depowering the bypassed elements. Controlling clock skew in this fashion improves operation of a computing device that includes the clock tree and may improve battery life.