发明名称 |
DRIVER FOR NORMALLY ON III-NITRIDE TRANSISTORS TO GET NORMALLY-OFF FUNCTIONALITY |
摘要 |
A semiconductor device includes a depletion mode GaN FET and an integrated driver/cascode IC. The integrated driver/cascode IC includes an enhancement mode cascoded NMOS transistor which is connected in series to a source node of the GaN FET. The integrated driver/cascode IC further includes a driver circuit which conditions a gate input signal and provides a suitable digital waveform to a gate node of the cascoded NMOS transistor. The cascoded NMOS transistor and the driver circuit are formed on a same silicon substrate. |
申请公布号 |
US2016277021(A1) |
申请公布日期 |
2016.09.22 |
申请号 |
US201615168458 |
申请日期 |
2016.05.31 |
申请人 |
Texas Instruments Incorporated |
发明人 |
PENDHARKAR Sameer;TIPIRNENI Naveen |
分类号 |
H03K17/687;H01L27/092;H01L29/66;H01L27/088;H01L29/20;H01L29/78 |
主分类号 |
H03K17/687 |
代理机构 |
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代理人 |
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主权项 |
1. A semiconductor device, comprising the steps of:
a depletion mode GaN FET; an integrated driver/cascode transistor IC having an upper cascode I/O port, a lower cascode I/O port, a gate I/O port, a Vss port, a VDD port, a Vcc port, and further including:
a cascoded NMOS transistor in a silicon substrate, the cascoded NMOS transistor having a drain connected to the upper cascade I/O port and a source connected to the lower cascode I/O port; anda driver circuit in said silicon substrate, so that a gate node of said cascoded NMOS transistor is connected to said driver circuit, wherein the driver circuit includes:
an edge detector circuit connected to the gate I/O port;a level shifter circuit connected to the edge detector circuit; anda driver buffer connected between the level shifter circuit and the cascoded NMOS transistor; an electrical connection between a drain node of said GaN FET and a drain terminal of said semiconductor device; an electrical connection between a source node of said GaN FET and the upper cascode I/O port; an electrical connection between a gate node of the GaN FET and the lower cascode I/O port; an electrical connection between the gate I/O port and a gate terminal of the semiconductor device; and an electrical connection between the Vss port and a Vss terminal of the semiconductor device. |
地址 |
Dallas TX US |