发明名称 Rapidly testable semiconductor memory device
摘要 A semiconductor memory device has an array of memory cells, an array of sense amplifiers selected at least two at a time by column lines, data bus lines that receive data read from the memory cell array by the selected sense amplifiers, a decision circuit that compares data read by two of the selected sense amplifiers, and an input-output buffer. Normally, the input-output buffer receives and outputs data from one or more of the data bus lines. In a test output mode, the input-output buffer receives and outputs comparison result data from the decision circuit. In a semiconductor memory device with multiple memory cell arrays, this arrangement enables data read from different memory cells in the same memory cell array to be compared, so that redundancy repair can be carried out efficiently.
申请公布号 US6868021(B2) 申请公布日期 2005.03.15
申请号 US20030669532 申请日期 2003.09.25
申请人 OKI ELECTRIC INDUSTRY CO., LTD. 发明人 TANABE TETSUYA;NASU NOBUTAKA
分类号 G11C29/00;G11C29/44;(IPC1-7):G11C7/00 主分类号 G11C29/00
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