| 摘要 |
PROBLEM TO BE SOLVED: To provide a highly reliable memory device capable of performing mutual communication between CPUs. SOLUTION: A CPU 100 can transfer data to a CPU 101 through, for example, an individual register 40 or a shared SRAM. In this case, data transfer from the CPU 100 to the CPU 101 through the individual register 40 is also executed through an FIFO 200. For example, when second data transfer through the individual register 40 is executed after first data transfer through the shared SRAM, since the second data transfer executed through the individual register 40 is also executed through the FIFO when the first data transfer is mediated by an SRAM controller to be made to wait in the FIFO 200, the data transfer can be properly completed without completing the second data transfer ahead of the first data transfer. Consequently, the reliability of the memory device can be improved. COPYRIGHT: (C)2008,JPO&INPIT
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