SHIFT REGISTER UNIT, ITS DRIVING METHOD, GATE DRIVER CIRCUIT AND DISPLAY DEVICE

摘要

A shift register unit includes an input end, a gate driving signal output end, a resetting end, a pull-up transistor, a pull-down transistor, a pull-down node control module, a pull-up node control module and an output noise reduction transistor. The pull-down node control module is configured to pull up a potential of a pull-down node to a high potential at a first noise reduction stage, so as to turn on the pull-down transistor and enable the gate driving signal output end to output a low level. The pull-up node control module is configured to pull down a potential of the pull-up node to a low potential at a resetting stage, and maintain the potential of the pull-up node to be at a low potential at the first noise reduction stage and a second noise reduction stage, so as to turn off the pull-up transistor.

主权项

1. A shift register unit, comprising an input end, a gate driving signal output end and a resetting end, further comprising:
a pull-up transistor, a gate electrode of which is connected to a pull-up node, a first electrode of which is configured to receive a first clock signal, and a second electrode of which is connected to the gate driving signal output end; a pull-down transistor, a gate electrode of which is connected to a pull-down node, a first electrode of which is connected to the gate driving signal output end, and a second electrode of which is configured to receive a first low level; a pull-down node control module configured to receive the first low level and the first clock signal, connected to the pull-up node and the pull-down node, and configured to control the pull-down node to be at a low potential at a pre-charging stage of each display period, maintain the pull-down node at the low potential at an outputting stage of each display period, pull up a potential of the pull-down node to a high potential at a first noise reduction stage of each display period so as to turn on the pull-down transistor, and thereby to enable the gate driving signal output end to output a low level; a pull-up node control module configured to receive a high level, the first low level and a second low level, connected to the pull-up node, the pull-down node, the input end and the resetting end, and configured to, pull up a potential of the pull-up node to a high potential at the pre-charging stage of each display period, control the potential of the pull-up node to be bootstrapped at the outputting stage of each display period so as to maintain the pull-up transistor in an on state and enable the gate driving signal output end to output the first clock signal, pull down the potential of the pull-up node to a low potential at a resetting stage of each display period, and maintain the pull-up node to be at a low potential at the first noise reduction stage and a second noise reduction stage of each display period so as to turn off the pull-up transistor; and an output noise reduction transistor, a gate electrode of which is configured to receive a second clock signal, a first electrode of which is connected to the gate driving signal output end, a second electrode of which is configured to receive the first low level, and which is configured to be turned on at the pre-charging stage, the resetting stage and the second noise reduction stage of each display period so as to perform noise reduction on the gate driving signal output end, thereby to enable the gate driving signal output end to output a low level, wherein the first clock signal is of a phase reverse to the second clock signal.