Time difference adders, time difference accumulators, sigma-delta time-to-digital converters, digital phase locked loops and temperature sensors

摘要

A time difference adder included in a system-on-chip (SOC) includes a first register unit and a second register unit. The first register unit is configured to receive first and second input signals having a first time difference, and generate a first output signal in response to a first signal. The second register unit is configured to receive third and fourth input signals having a second time difference, and generate a second output signal having a third time difference with respect to the first output signal in response to the first signal. The third time difference corresponds to a sum of the first time difference and the second time difference.

主权项

1. A sigma-delta time-to-digital converter, comprising:
a time difference adder configured to receive first and second input signals having a first time difference, the time difference adder being further configured to subtract a second time difference between first and second feedback signals from the first time difference to generate first and second addition signals having a third time difference corresponding to the first time difference minus the second time difference; a time difference accumulator configured to accumulate the third time difference between the first and second addition signals to generate first and second accumulation signals; a time domain quantizer configured to convert a time difference between the first and second accumulation signals into a digital output signal; and a digital-to-time converter configured to convert the digital output signal into the first and second feedback signals.