发明名称 Clock supply circuit layout in a circuit area
摘要 A clock supply circuit having a circuit area includes an input terminal for receiving a clock pulse and a buffer having an input electrically connected to the input terminal and an output. The buffer is disposed in the center of the circuit area. The clock supply circuit also includes a main conductive pattern electrically connected to the output of the buffer. The main conductive pattern is disposed through the center of the circuit area. Each of the branch conductive patterns is electrically connected to the main conductive pattern and extends from the main conductive pattern. Also, each of the branch conductive patterns has a width smaller than the width of the main conductive pattern. Each of the clock receiving circuits is electrically connected to one of the branch conductive patterns and disposed in the circuit area. The number of the clock receiving circuits electrically connected to one branch conductive pattern is same.
申请公布号 US5270592(A) 申请公布日期 1993.12.14
申请号 US19920933345 申请日期 1992.08.21
申请人 OKI ELECTRIC INDUSTRY CO., LTD. 发明人 TAKAHASHI, TADAO;YAMAMOTO, ICHIRO;FUKUYAMA, HIROYUKI
分类号 H01L21/82;G06F1/10;H01L21/822;H01L23/522;H01L27/04;H03K19/00;H03K21/02;(IPC1-7):H03K19/01;H03K5/13 主分类号 H01L21/82
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