发明名称 Buffer control system
摘要 A buffer control system is a system for implementing both a priority control process and a shaping process of cells with a hardware configuration of a small size in a network routing fixed-length packets which are respectively composed of transfer data and control information added to the transfer data, and to which priority information is assigned, according to the control information. If a cell written to an empty area of a cell buffer 26 is a prioritized cell, and its expected output time is a time slot 6, an address where the cell is stored in the cell buffer 26 is arranged in a time slot 6 in a prioritized cell entry memory. When it reaches the time to read the cell stored in the time slot 6, address stored in the time slot 6 is written to an output list chain, and the cell is read from that address. The empty area of the buffer is managed using a free list chain. <IMAGE>
申请公布号 EP0753981(A2) 申请公布日期 1997.01.15
申请号 EP19960305023 申请日期 1996.07.08
申请人 FUJITSU LIMITED 发明人 OKUDA, MASATO;SUDO, TOSHIYUKI;ISHIHARA, TOMOHIRO;KUSAYANAGI, MICHIO
分类号 H04Q3/00;H04L12/741;H04L12/815;H04L12/823;H04L12/835;H04L12/863;H04L12/865;H04L12/879 主分类号 H04Q3/00
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