发明名称 |
Schaltung zur Verarbeitung eines Videosignals |
摘要 |
Interpolated scan lines are produced in response to received video signals which are comprised of conventional interlaced scan lines constituting successive fields. A delay circuit 501y,502y,503y; 501C,502C,503C, preferably formed of field memory devices, such as three cascaded field memories, functions to delay the received video signals to provide a first scanned line signal b in a given field, the next succeeding scan line signal c in that field, an interlaced scan line signal a in the next succeeding field and an interlaced scan line signal d in the next preceding field. A first combining circuit 504y,504C combines the signal values of the next succeeding field interlaced scan line signal a and the next preceding field interlaced scan line signal d to form a first combined scan line signal. A second combining circuit 505y;505C combines the signal values of the first scan line signal b in the given field and the next succeeding scan line signal c in that field to form a second combined scan line signal. The first and second combined scan line signals are level adjusted and added to produce an interpolated scan line signal yc;Rc-yc/Bc-yc intermediate successive main scan lines in the given field. <IMAGE> |
申请公布号 |
DE68927597(D1) |
申请公布日期 |
1997.02.13 |
申请号 |
DE1989627597 |
申请日期 |
1989.07.18 |
申请人 |
SONY CORP., TOKIO/TOKYO, JP |
发明人 |
MOTOE, HISAFUMI, SHINAGAWA-KU TOKYO, JP;KAWASHIMA, HIROYUKI, SHINAGAWA-KU TOKYO, JP;TOKUHARA, MASAHARU, SHINAGAWA-KU TOKYO, JP |
分类号 |
H04N7/01;H04N11/20 |
主分类号 |
H04N7/01 |
代理机构 |
|
代理人 |
|
主权项 |
|
地址 |
|