发明名称
摘要 PURPOSE:To carry out a 2nd instruction code with input of a 1st instruction code by producing the address information from the 1st instruction code and the decoding information received from a decoding circuit and producing the 2nd instruction code from said address information to send this 2nd instruction code to the decoding circuit. CONSTITUTION:In case an instruction code contains two bytes, both a page designating signal 110 and a 2-byte instruction deciding signal 109 are inactive and a conversion memory 102 is read out in a read state of the 1st byte of a 1st instruction code. Then an instruction decoding circuit decides that a conversion instruction code is equal to the 1st byte of a 2-byte instruction of the 1st instruction code. Thus the signal 10 is activated. An address control circuit 103 produces a read address of the memory 102 from the signal 110 and the 2nd byte instruction code of the 1st instruction code. Then the 1st byte of the 2nd instruction code is read out of the memory 102. When an instruction decoding process is carried out by the circuit 108, the signal 109 is activated and the circuit 103 produces a read address of the 2nd byte. Then the 2nd byte of the 2nd instruction code is read out of the memory 102.
申请公布号 JP2684664(B2) 申请公布日期 1997.12.03
申请号 JP19880008762 申请日期 1988.01.18
申请人 发明人
分类号 G06F12/14;G06F9/06;G06F21/22;G06F21/24 主分类号 G06F12/14
代理机构 代理人
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