发明名称 Clock recovery circuit
摘要 A phase locked loop, which does not require a local reference clock to obtain a frequency lock. The circuit includes a frequency locked loop and a phase locked loop in which the frequency locked loop does not require a local reference clock. The frequency locked loop includes a transition counter having an input for data with an output connected to a charge pump. This charge pump is connected to a loop filter, which in turn is connected to a voltage controlled oscillator. The output of the voltage controlled oscillator is connected to a second input in the transition counter. The phase locked loop includes a phase detector with an input for data. The output of this phase detector is connected to a second charge pump, which has it output connected to the loop filter. The output of the voltage controlled oscillator also is connected to the input of the phase detector.
申请公布号 US5987085(A) 申请公布日期 1999.11.16
申请号 US19970824170 申请日期 1997.03.26
申请人 LSI LOGIC COPORATION 发明人 ANDERSON, MICHAEL B.
分类号 H03L7/113;H04L7/033;(IPC1-7):H03D3/24 主分类号 H03L7/113
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