发明名称 DELAY LOCK LOOP WITH CLOCK PHASE SHIFTER
摘要 A delay lock loop uses a clock phase shifter with a delay line to synchronize a reference clock signal with a skewed clock signal. The delay line is coupled to a reference input terminal of the delay lock loop and generates a delayed clock signal that is provided to the clock phase shifter. The clock phase shifter generates one or more phase-shifted clock signals from the delayed clock signal. An output generator coupled to the delay line, the clock phase shifter, and an output terminal of the delay lock loop provides either the delayed clock signal or one of the phase-shifted clock signals as an output clock signal of the delayed lock loop. The propagation delay of the delay line is set to synchronize the reference clock signal with the skewed clock signal, which is received on a feedback input terminal of the delay lock loop. A phase detector compares the reference clock signal and the skewed clock signal to determine the appropriate propagation delay for the delay line.
申请公布号 WO9967882(A1) 申请公布日期 1999.12.29
申请号 WO1999US07775 申请日期 1999.04.09
申请人 XILINX, INC. 发明人 HASSOUN, JOSEPH, H.;GOETTING, F., ERICH;LOGUE, JOHN, D.
分类号 G06F1/10;H03K5/13;H03L7/07;H03L7/081;(IPC1-7):H03L7/081 主分类号 G06F1/10
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