Co-verification—of hardware and software, a unified approach in verification

摘要

A co-verification method and system are described herein. The co-verification method is able to verify software and hardware at the same time. Constraints are provided to a software compiler which generates programming values. The programming values and stimulus from a verification test bench are utilized to test a design such as a microprocessor.

主权项

1. A method of co-verification of a compiler and a device under test within a test bench verification environment implemented by a test bench, the method comprising:
providing verification constraint information including code to implement one or more desired design features for the device under test; compiling the verification constraint information with the compiler to generate programming values for the device under test; generating the device under test within the test bench verification environment based on the programming values produced by the compiler such that the device under test operates according to the programming values; and performing verification tests on the device under test to test one or more of the desired design features using stimulus from the test bench thereby testing both the compiler and the device under test.