Thin film transistor, method of manufacturing the same, display substrate and display apparatus

摘要

A thin film transistor is disclosed in the present invention. The thin film transistor comprises: a substrate, an active layer, a first etching barrier layer, a second etching barrier layer, a source and a drain, wherein: the active layer is disposed over the substrate; the first etching barrier layer is disposed over the active layer; the second etching barrier layer is disposed over the first etching barrier layer; the source and the drain are disposed over the second etching barrier layer, and are connected to each other through the active layer by means of via holes formed in the first etching barrier layer and the second etching barrier layer by etching; and a length of the first etching barrier layer at a channel position is less than a length of the second etching barrier layer. A method of manufacturing the thin film transistor, an array substrate and a display apparatus are also disclosed in the present invention. A length of a channel of the thin film transistor according to the present invention is less than the length of the channel of the conventional thin film transistor. Thereby, size and energy consumption of the thin film transistor are reduced, an aperture ratio of a liquid crystal panel is increased, and a turn-on current of the thin film transistor is increased, so that whole performance of the thin film transistor is further improved.

主权项

1. A thin film transistor comprising: a substrate, an active layer, a first etching barrier layer, a second etching barrier layer, a source and a drain, wherein:
the active layer is disposed over the substrate; the first etching barrier layer is disposed over the active layer; the second etching barrier layer is disposed over the first etching barrier layer; the source and the drain are disposed over the second etching barrier layer, and are connected to each other through the active layer by means of via holes which are formed in the first etching barrier layer and the second etching barrier layer by etching; and a length of the first etching barrier layer at a channel position is less than a length of the second etching barrier layer at the channel position.