发明名称 |
Stress release layout and associated methods and devices |
摘要 |
An embodiment semiconductor device includes a substrate such as a silicon or silicon-containing film, a pixel array supported by the substrate, and a metal stress release feature arranged around a periphery of the pixel array. The metal stress release feature may be formed from metal strips or discrete metal elements. The metal stress release feature may be arranged in a stress release pattern that uses a single line or a plurality of lines. The metal stress release pattern may also use metal corner elements at ends of the lines. |
申请公布号 |
US9478578(B2) |
申请公布日期 |
2016.10.25 |
申请号 |
US201514923148 |
申请日期 |
2015.10.26 |
申请人 |
Taiwan Semiconductor Manufacturing Company, Ltd. |
发明人 |
Jeng Chi-Cherng;Chou Chun-Hao;Tsai Tsung-Han;Lee Kuo-Cheng;Chien Volume;Ho Yen-Hsung;Tseng Allen |
分类号 |
H01L27/146;H01L31/18 |
主分类号 |
H01L27/146 |
代理机构 |
Slater Matsil, LLP |
代理人 |
Slater Matsil, LLP |
主权项 |
1. A semiconductor device, comprising:
a substrate, the substrate having a device region and a periphery region; one or more metal stress release features on the periphery region of the substrate; and an interlayer dielectric layer over the device region and the one or more metal stress release features, the interlayer dielectric layer being a lowermost interlayer dielectric layer. |
地址 |
Hsin-Chu TW |