Fast semantic processor for Per-pin APG

摘要

System and method for implementing a memory test language compiler. The compiler includes a fast semantic processor for interpreting programming patterns in a test program, including converting stateful patterns into stateless patterns, and a device access timing generation module for generating an output based on the stateless patterns. The fast semantic processor can generate a closure for a device access line as the output. In the state of the closure, each device access line is in a closed state. A functor is formed from the interdependency of the variables and the loop dependency and a cache is used to handle recursive variables. The functor is propagated to device access lines as output, wherein the functor references the cache when needed.

主权项

1. A non-transitory computer-readable storage medium embodying instructions that, when executed by a processing device, implements a test program compiler, said test program compiler comprising:
a fast semantic processor configured to perform interpreting of programming test patterns for testing an integrated circuit through an automated test equipment (ATE), wherein the test patterns are contained in a test program, wherein the interpreting comprises converting stateful patterns into stateless patterns; and a device access timing generation module configured to generate an output based on the stateless patterns, wherein the output is executable by a test processor to generate a binary sequence for testing an integrated circuit device, wherein the fast semantic processor is free of recursive calculation of recursive variables.