| 摘要 |
A semiconductor memory device comprises active pull-up circuits (APU1, APU2) each provided for one bit line (BL1, &upbar& B1). Each active pull-up circuit (APU1) has connections to two bit lines. That is, an active pull-up circuit (APU1) for a first bit line (BL1) comprises a first transistor (Q1) connected between a power supply terminal (VCC) and the first bit line, a second transistor (Q2) connected between the gate of the first transistor and the first bit line, and a capacitor (C1) connected to the gate of the first transistor. The gate of the second transistor is connected to a second bit line ( &upbar& B1) which is paired with the first bit line. The capacitor receives an active pull-up signal ( phi AP). A circuit (Q3, Q4, Q5) is provided for transmitting a high level potential to the gate (N1) of the first transistor to precharge the capacitor.
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