发明名称 FLIP-FLOP CIRCUIT FOR SCAN PASS TEST
摘要 PROBLEM TO BE SOLVED: To improve an operating speed. SOLUTION: In a normal operation mode, a control signal sc is set to '1', a control signal scn is set to '0', and a scan data receiving clocked inverter 24 is set to an off-state and separated from a node 25. Clocked inverters 23, 26b, 27 and 28b are turned on and off by control signals dc, dcn, c and cn to receive the normal data DI and to output the data at the prescribed timing. In a shift mode of a scan pass test, the control signal dc is set to '1', the control signal dcn is set to '0', and the data receiving clocked inverter 23 is set to an off-state and separated from the node 25. The inverters 24, 26b, 27 and 28b are turned on and off by the control signals sc, scn, c and cn to receive the scan data SI and to output the data at the prescribed timing.
申请公布号 JP2001324544(A) 申请公布日期 2001.11.22
申请号 JP20000143247 申请日期 2000.05.16
申请人 OKI ELECTRIC IND CO LTD 发明人 TOKUNO YOSHIO
分类号 G01R31/28;H03K3/037;(IPC1-7):G01R31/28 主分类号 G01R31/28
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