| 摘要 |
The programmable decoder, such as a Maximum Likelihood Sequence Estimatio n (MLSE) decoder (e.g., a Viterbi decoder) may include a programming input f or a plurality of programmable trellis parameters, and a programmable device , such as an FPGA, connected to the programming input and implementing a con tinuous phase modulation (CPM) decoder including at least one trellis struct ure defined based upon the plurality of programmable trellis parameters. The plurality of programmable trellis parameters may include a number of trelli s structures, a number of trellis states for each trellis structure, and a n umber of branches for each trellis state. Also, the trellis structure may in clude a reverse-state trellis structure.
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