| 摘要 |
Methods, systems, and apparatuses for semiconductor wafers and integrated circuit chip packaging techniques are provided. A wafer is fabricated that supports multiple different packaging techniques. The wafer is formed to have a plurality of integrated circuit regions. A first plurality of terminals is formed on a surface of the wafer in a central region of each integrated circuit region. A second plurality of terminals is formed on the surface of the wafer in a peripheral region of each integrated circuit region. For each integrated circuit region, each terminal of the second plurality of terminals is electrically coupled through the wafer to at least one terminal of the first plurality of terminals. The integrated circuit regions can be separated into chips that can be packaged in multiple ways. In an aspect, a wafer may be fabricated that supports wire-bond packaging or wafer level ball grid array (WLBGA) packaging for a common chip/die configuration of the wafer. |
