| 摘要 |
PROBLEM TO BE SOLVED: To provide a junction FET having a great noise margin for a gate. SOLUTION: The junction FET 1 includes a n<SP>-</SP>layer 11 in a drift region of the junction FET 1, formed on the main face of n<SP>+</SP>substrate 12 of silicon carbide, a p<SP>+</SP>layer 9 in a gate region, joined and formed onto the n<SP>-</SP>layer 11 in the drift region, and a gate electrode 14 provided on the upper layer of the n<SP>+</SP>substrate 12. The junction FET 1 has a built-in pn diodes 2, 3 formed on the main face of the n<SP>+</SP>substrate 12 to electrically connect the p<SP>+</SP>layer 9 in the gate region to the gate electrode 14. COPYRIGHT: (C)2009,JPO&INPIT |
