发明名称 Semiconductor package with embedded die
摘要 A semiconductor package having an embedded die and solid vertical interconnections, such as stud bump interconnections, for increased integration in the direction of the z-axis (i.e., in a direction normal to the circuit side of the die). The semiconductor package can include a die mounted in a face-up configuration (similar to a wire bond package) or in a face-down or flip chip configuration.
申请公布号 US9385074(B2) 申请公布日期 2016.07.05
申请号 US201313935053 申请日期 2013.07.03
申请人 STATS ChipPAC Pte. Ltd. 发明人 Pendse Rajendra D.
分类号 H01L23/498;H01L23/31;H01L23/00;H01L25/10;H01L21/56 主分类号 H01L23/498
代理机构 Patent Law Group: Atkins and Associates, P.C. 代理人 Atkins Robert D.;Patent Law Group: Atkins and Associates, P.C.
主权项 1. A method of making a semiconductor device, comprising: providing a semiconductor die; forming a conductive layer in a peripheral region around the semiconductor die; and forming a first stud bump over the conductive layer by pressing a wire over the conductive layer under temperature to flatten an end of the wire and form an enlarged base portion covering a top surface and side surface of the conductive layer.
地址 Singapore SG