发明名称 Efficient High-Radix Networks for Large Scale Computer Systems
摘要 An interconnection method is disclosed for connecting multiple sub-neworks providing significant improvements in performance and reductions in cost. The method interconnects copies of a given sub-network, e.g., a 2-hop Moore graph sub-network, or a 2-hop Flattened Butterfly sub-network. Each sub-network connects to every other sub-network over multiple links, and the originating nodes in each sub-network lie at a maximum distance of 1 hop from all other nodes in that sub-network. This set of originating nodes connects to a set of similarly chosen nodes in another sub-network, for each pair of sub-networks, to produce a system-wide diameter of 4 (maximum of 4 hops between any two nodes), given 2-hop sub-networks. For example, to reach a given remote sub-network j, starting at a node in sub-network i, a packet must first reach any one of the local sub-network i's originating nodes, connected to nodes in remote sub-network j. This takes at most one hop. Another hop reaches the remote sub-network j, where it takes at most two hops to reach the desired node. The disclosed interconnection methodology scales up to billions of nodes in an efficient manner, keeping the number of required ports per router low, the number of hops to connect any given pair of nodes low, the bisection bandwidths high, and it provides easily determined routing. Moreover, because each sub-network can be identical, only one PCB design for the subnet needs to be designed, tested, and manufactured. All of these design features significantly reduce costs and while also significantly increasing performance.
申请公布号 US2016285741(A1) 申请公布日期 2016.09.29
申请号 US201615130957 申请日期 2016.04.16
申请人 Jacob Bruce Ledley 发明人 Jacob Bruce Ledley
分类号 H04L12/715;H04L12/707;H04L12/727;H04L12/755;H04L12/703 主分类号 H04L12/715
代理机构 代理人
主权项 1. A multiprocessing network, comprising: multiple processing nodes, each node having multiple ports; the ports connecting their node to the ports of other processing nodes; the network divided into sub-networks, each sub-network having substantially the same topology so that one sub-network circuit-board design can be used for all sub-networks; and the sub-networks connected in a scalable Moore graph network topology.
地址 Arnold MD US